Semiconductor device designers often desire to increase the level of integration or density of features within a semiconductor device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, semiconductor device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.
A relatively common semiconductor device is a memory device. A memory device may include a memory array having a number of memory cells arranged in a grid pattern. One type of memory cell is a dynamic random access memory (DRAM). In the simplest design configuration, a DRAM cell includes one access device, such as a transistor, and one storage device, such as a capacitor. Modern applications for memory devices can utilize vast numbers of DRAM unit cells, arranged in an array of rows and columns. The DRAM cells are electrically accessible through digit lines and word lines arranged along the rows and columns of the array.
Reducing the dimensions and spacing of memory device features places ever increasing demands on the methods used to form the memory device features. For example, one of the limiting factors in the continued shrinking of memory devices is the resistance of the contacts associated therewith. As used herein, a “contact” refers to a connection facilitating a conductive pathway between at least two structures. For example, in a DRAM device exhibiting a dual bit memory cell structure, a digit line contact is provided between a digit line and an access device (e.g., a transistor) formed in or above a substrate, and storage node contacts are formed between the access device and a storage node (e.g., a capacitor) where electrical charge may be stored. As the dimensions of memory device (e.g., DRAM device) features decrease, the dimensions of the contacts associated therewith also decrease, resulting in increased contact resistance. Increased contact resistance decreases the drive current of the memory device, which can adversely affect memory device performance.
One approach toward decreasing contact resistance within a memory device has been to increase the surface area of the contacts thereof. For example, material may be removed from multiple surfaces of a memory device feature to form a three dimensional (3D) contact exhibiting greater contact surface area than the memory device feature would otherwise exhibit. Unfortunately, conventional methods of forming such 3D contacts can suffer from a variety of problems. For example, conventional methods of forming 3D contacts for a DRAM device structure exhibiting lower critical dimensions, such as critical dimensions less than about 20 nanometers (nm), can require complex and costly processes to sufficiently form and align 3D storage node contacts relative to digit line contacts to ensure proper performance of the DRAM device. If, for example, a contact hole in which a digit line contact (e.g., a doped polysilicon plug) is formed does not completely expose an active area of a semiconductive pillar associated with the digit line contact, or extends into storage node contact regions of neighboring semiconductive pillars, the DRAM device may short during use and operation. In addition, conventional methods of forming 3D contacts for a DRAM device structure may also require increased feature dimensions, such as thicker nitride caps over digit lines, to account for material (e.g., silicon nitride) loss associated with dry etching processes (e.g., reactive ion etching processes) required to form the 3D contacts.
A need, therefore, exists for new, simple, and cost-efficient methods of forming contacts for a semiconductor device structure, such as, for example, a DRAM device structure including features having critical dimensions less than about 20 nm.